As the frequencies of modern computers continue to increase, the need to rapidly transmit data between chip interfaces also increases. To accurately receive data, a clock signal is often transmitted to help recover the data. The clock signal determines when the data signal should be sampled by a receiver's circuits.
The transmitted clock signal may transition at the beginning of the time the data is valid; however, the receiver's circuits should latch the data during the middle of the time the data is valid. Also, the transmission of the clock signal may degrade as it travels from its transmission point. In both circumstances, a delay locked loop, or DLL, can regenerate a copy of the clock signal at a fixed phase shift from the original.
FIG. 1 shows a block diagram of a typical communication system (10). The communication system (10) includes multiple links. Each link may include multiple data lines and an associated clock line. Data lines (14) that are N bits wide connect between circuit A (12) and circuit B (34). To aid in the recovery of transmitted data on the data lines (14), a clock signal on clock line A (16) is transmitted with data signals on the data lines (14). Another link includes data lines (24) that are M bits wide and a clock line Z (26). A clock signal on the clock line Z (26) is transmitted with data signals on the data lines (24) to determine when the data signals on the data lines (24) should be latched.
Data signals on the data lines (14, 24) are transmitted from circuit A (12) to circuit B (34). Circuit A (12) and circuit B (34) could also have one or more links to transmit data from circuit B (34) to circuit A (12) along with one or more additional clock signals (not shown).
The data signals and clock signals transmit information from circuit A (12) to circuit B (34) under the direction of control signals. The control signals are transmitted between circuit A (12) and circuit B (34) on control lines (32) that are K bits wide. The control signals may determine on which cycle, what frequency, and/or under which operating mode the data signals and clock signals should be transmitted. The control signals may carry a request that circuit A (12) transmit a predetermined test pattern to circuit B (34) to test and improve transmission across the link.
In FIG. 2, a block diagram of a typical receiver (200) is shown. A clock signal (201) is input to a DLL (252) in order for the DLL (252) to generate a phased output, clk_out signal (213). The clk_out signal (213) from the delay locked loop (252) provides a phase delayed copy of the clock signal (201) to other circuits (i.e., clk_out signal (213)).
The data signals on data (217) through data line V (219) arrive at flip-flop (212) through flip-flop (214), respectively. The data signals on data line 1 (217) through data line V (219) are latched depending on the arrival time of the clk_out signal (213) to generate latched data signals on chip_data line 1 (221) through chip_data line V (223), respectively. Depending on the arrival time of the clk_out signal (213), some or all of the latched data signals may not equal the same state as the data signals on data line 1 (217) through data line V (219).
A test circuit (290) is used to improve the link efficiency. The test circuit (290) tests and adjusts the link in response to a test signal (299). The test circuit (290) is used to test and improve transmission across the link that includes clock signal (201) and data lines (217, 219). A predetermined test pattern signal is transmitted on the data lines (217, 219) under the direction of the control signals (227) that are S bits wide. As mentioned earlier, the test pattern signal is latched by the flip-flops (212, 214) based on the clk_out signal (213). The resulting latched test pattern signals on chip_data (221) through chip_data line V (223) are compared with the predetermined test pattern signal by the test circuit (290).
In FIG. 2, the test circuit (290) controls and coordinates the activities of the test sequence. The test circuit (290) adjusts the clk_out signal (213) to select a timing of the clk_out signal (213) relative to the test pattern signals on data line 1 (217) through data line V (219). The latched test pattern signals on chip_data line 1 (221) through chip_data line V (223) are compared with the test pattern signal by the test circuit (290) to determine whether the latched test pattern signals are the same as the test pattern signals.
The test circuit (290) may select a different delay value for the clk_out signal (213) and repeat the transmission of the test pattern signal, the latching of the test pattern signal, and the comparing of the test pattern signal to the latched test pattern signal. A set of tests with different selected delay values for the clk_out signal (213) may indicate a best selected delay value or a range of selected delay values for the clk_out signal (213). The test circuit (290) fixes the selected delay value for the clk_out signal (213) to improve transmission across the link. Data signals transmitted across the link under non-test conditions may have a higher probability of successful transmission after the delay value of the clk_out signal (213) is appropriately selected.
In FIG. 3, an exemplary timing diagram (300) is shown for one clock cycle of a test pattern signal on one data line (301). Multiple offset values are added to a clock signal to generate multiple adjustable clock signals (303, 305, 307, 309, 311, 313, 315) relative to the one clock cycle of the test pattern signal. The test pattern signal is latched according to a rising edge of the adjustable clock signal (303, 305, 307, 309, 311, 313, or 315). A rising edge of each of the multiple adjustable clock signals (303, 305, 307, 309, 311, 313, 315) is indicated by the vertical lines (321, 323, 325, 327, 329, 331, 333), respectively.
The adjustable clock signals (303, 305, 313, 315) and signal on the data line (301) may jitter. Because the adjustable clock signals (303, 305, 313, 315) are temporally located near the beginning or end of the test pattern signal transmission, the latched test pattern signal may not be correct (i.e., a fail). The setup and hold times for the latch are not satisfied. Because the adjustable clock signals (307, 309, 311) are temporally located near the middle of the test pattern signal transmission, the latched test pattern signal may be correct (i.e., a pass). The pass (P) or fail (F) condition is shown as comparison results (317). The pass (P) or fail (F) condition for a link may be based on tests of multiple data lines, multiple cycles of test patterns, and/or repeated test patterns.
The testing of a link is performed during the power-on reset of a central processing unit (CPU) or, more generally, an integrated circuit. Once the value for the offset signal has been determined, it is fixed for the duration of the CPU operation until power is removed or cycled. As the communication system characteristics change due to temperature, voltage, and/or aging effects, the delay value for the clk_out signal (213 in FIG. 2) may not maintain a desired temporal position to latch the incoming data.